1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor integrated circuit including simultaneous formation of a via hole reaching a metal wiring and a concave groove in an interlayer film, and a semiconductor integrated circuit manufactured with the manufacturing method.
2. Description of the Relate Art
In recent years, higher performance and finer size are required for semiconductor integrated circuits, and various manufacturing methods and materials for use are under study. Conventionally, polysilicon and aluminum have often been used for wirings in the semiconductor integrated circuits. However, materials with lower resistance are needed to realize higher performance and finer size of the semiconductor integrated circuits.
To address such a need, the use of copper has been proposed to form fine wirings in a semiconductor integrated circuit. However, copper has properties which make patterning with etching difficult, and has low corrosion resistance. Thus, a dual damascene method has been developed as a method of manufacturing a semiconductor integrated circuit in which metal wirings made of copper are formed within and on a surface of an interlayer film and the metal wirings are connected to each other with a contact made of copper.
A prior art of the method of manufacturing a semiconductor integrated circuit with the dual damascene method is hereinafter described with reference to FIG. 1A to FIG. 4C. The drawings of FIG. 1A to FIG. 4C are front section views sequentially showing manufacturing steps of a semiconductor integrated circuit.
First, semiconductor integrated circuit 100 to be manufactured in this case is described. As shown in FIG. 4C, semiconductor integrated circuit 100 comprises lower interlayer film 101 made from SiO2 and upper interlayer film 102. Upper interlayer film 102 is disposed on stopper film 115 layered on the surface of the lower interlayer film 101. Lower metal wiring 103 made of copper is embedded in an upper portion of lower interlayer film 101. Upper metal wiring 104 made of copper is also embedded in an upper portion of upper interlayer film 102, and connecting wiring 105 formed integrally with upper metal wiring 104 is connected to lower metal wiring 103.
Lower metal wiring 103 and upper metal wiring 104 extend, for example, in a direction passing through the drawing (hereinafter referred to as xe2x80x9cfront-to-back directionxe2x80x9d). Connecting wiring 105 is formed to have the front-to-back length identical to the left-to-right width, for example. Connecting wiring 105 which does not extend in the front-to-back direction connects lower metal wiring 103 to upper metal wiring 104 at one point.
As a typical method of manufacturing semiconductor integrated circuit 100 configured as described above, as shown in FIG. 1A, lower interlayer film 101 made from SiO2 with a predetermined thickness is formed on a surface of silicon substrate 100, and a photoresist (not shown) is applied on the surface thereof and then patterned to form a resist mask (not shown). Lower interlayer film 101 is dry etched through an opening in the resist mask, thereby forming concave 111 with a predetermined depth on the surface of lower interlayer film 101 as shown in FIG. 1B.
After concave 111 is completed, the resist mask is removed with plasma processing and organic removal in an atmosphere of O2. Then, as shown in FIG. 1C, tantalum film 112 and copper film 113 are sequentially formed with sputtering on the surface of exposed lower interlayer film 101.
Next, as shown in FIG. 1D, plating film 114 made of copper is formed on the surface of copper film 113 to fill concave 111. As shown in FIG. 1E, plating film 114, copper film 113, and tantalum film 112 are polished flatly with CMP (Chemical Mechanical Polishing) until the surface of lower interlayer film 101 is exposed.
Next, as shown in FIG. 2A, stopper film 115 made from SiN is grown to have a thickness of 500 [xc3x85], for example, on the surface of the flatly polished surface with a plasma CVD (Chemical Vapor Deposition) process. Then, upper interlayer film 102 made from SiO2 is grown to have a thickness of 12000 [xc3x85], for example, on the surface of stopper film 115 with the plasma CVD process.
Resist mask 116 with an opening above upper metal wiring 103 is then formed on the surface of upper interlayer film 102, and upper interlayer film 102 is etched through the opening in resist mask 116, thereby forming via hole 117 extending from the surface of upper interlayer film 102 to the surface of stopper film 115 at the position opposite to lower metal wiring 103.
Resist mask 116 is removed after via hole 117 is formed. As shown in FIG. 2C, ARC (Anti Reflective Coating) film 118 serving as an organic film is formed to have a thickness of 2000 [xc3x85] on the surface of upper interlayer film 102, and the material of ARC film 118 is filled in via hole 117.
Resist mask 119 with an opening wider than via hole 117 is formed to have a thickness of 8000 [xc3x85], for example, on the surface of ARC film 118. Then, in an atmosphere where an etching gas formed by mixing xe2x80x9cC4F8xe2x80x9d and xe2x80x9cO2,xe2x80x9d and an inert gas including xe2x80x9cArxe2x80x9d are maintained at a pressure of approximately 30 [mTorr], ARC film 118 is plasma etched through the opening in resist mask 119 as shown in FIG. 2D. The mixing ratio of xe2x80x9cC4F8xe2x80x9d:xe2x80x9cO2xe2x80x9d:xe2x80x9cArxe2x80x9d is xe2x80x9c20:10:200xe2x80x9d, for example.
After ARC film 118 is plasma etched, the etching gas is changed to xe2x80x9cC4F8xe2x80x9d only, and as shown in FIG. 3A, ARC film 118 and upper interlayer film 102 are simultaneously plasma etched through the opening in resist mask 119 to form concave groove 120 which is wider than via hole 117. The depth of concave groove 120 is 4000 [xc3x85] which does not reach stopper film 115.
At this point, since the etching rate of the plasma etching of upper interlayer film 102 and ARC film 118 with the etching gas including xe2x80x9cC4F8xe2x80x9d is approximately xe2x80x9c4000 xc3x85/min,xe2x80x9d the depth of concave groove 120 can be adjusted to 4000 [xc3x85] by performing the etching for 1 minute.
Next, by means of plasma processing with xe2x80x9cO2xe2x80x9d and removal processing with an amine organic remover, resist mask 119 and ARC film 118 are removed as shown in FIG. 3B to expose stopper film 115 at the bottom of via hole 117. It should be noted that while lower metal wiring 103 made of copper has low corrosion resistance, it is not subjected to corrosion since lower metal wiring 103 is shielded from surrounding environments by stopper film 115 when resist mask 119 and ARC film 118 are removed as described above.
Subsequently, in an atmosphere of an etching gas formed by mixing xe2x80x9cCHF3xe2x80x9d and xe2x80x9cO2,xe2x80x9d and an inert gas including xe2x80x9cAr,xe2x80x9d stopper film 115 exposed at the bottom of via hole 117 is plasma etched with upper interlayer film 102 used as a mask to expose lower metal wiring 103 at the bottom of via hole 117 as shown in FIG. 3C. The mixing ratio of xe2x80x9cCHF3xe2x80x9d:xe2x80x9cO2xe2x80x9d:xe2x80x9cArxe2x80x9d is also xe2x80x9c20:10:200xe2x80x9d, for example.
In this state, the exposed surfaces of upper interlayer film 102 and lower metal wiring 103 are cleaned with an amine organic remover, and as shown in FIG. 4A, tantalum nitride film 121 and copper film 122 are sequentially formed on the cleaned surfaces with sputtering. Thus, tantalum nitride film 121 and copper film 122 are formed to cover the upper surface of upper interlayer film 102 and the inner surfaces of concave groove 120 and via hole 117.
Then, as shown in FIG. 4B, plating film 123 made of copper is formed on the surface of copper film 122. At this point, the material of plating film 123 is filled in concave groove 120 and via hole 117.
Plating film 123, copper film 122, and tantalum nitride film 121 are flatly polished with the CMP until the surface of upper interlayer film 102 is exposed, thereby upper metal wiring 104 embedded in concave groove 120 and connecting wiring 105 embedded in via hole 117 are formed as shown in FIG. 4C. With the aforementioned steps, semiconductor integrated circuit 100 is completed.
The approach for simultaneously forming via hole 117 with a relatively small width and concave groove 120 with a relatively large width is usually called a dual damascene method. For the aforementioned interlayer films 101 and 102, a film with a low permittivity may be used other than the SiO2 films. For the film with a low permittivity, a hydrogen-containing silicon oxide film or an organic substance-containing silicon oxide film may be used.
For the material of ARC film 118, polyvinylphenol or polymethylmetacrylate added to a base resin made from polyimide or novolac may be used. For the material of the resist, a novolac resin or a polyimide resin may be used.
The manufacturing of semiconductor integrated circuit 100 with the aforementioned method enables concave groove 120 with a relatively large width to be formed on via hole 117 with a relatively small width. Thus, it is possible to form a structure in which lower metal wiring 103 made of copper embedded in lower interlayer film 101 is connected to upper metal wiring 104 made of copper embedded in upper interlayer film 102 through connecting wiring 105 in via hole 117.
However, when ARC film 118 and upper interlayer film 102 are simultaneously plasma etched with the etching gas including xe2x80x9cC4F8xe2x80x9d as shown in FIG. 3A, the etching rate for ARC film 118 is actually lower than that of upper interlayer film 102. Thus, the plasma etching proceeds in a state in which ARC film 118 projects from the surface of upper interlayer film 102 at the bottom of concave groove 120.
In addition, the etching gas including xe2x80x9cC4F8xe2x80x9d is likely to produce deposition of fluorocarbon base from what is decomposed in the plasma or a reaction product. Thus, if the plasma etching proceeds in a state in which ARC film 118 projects from the surface of upper interlayer film 102 at the bottom of concave groove 120 as described above, depositions 124 tend to accumulate on the sides of ARC film 118 projecting from the surface of upper interlayer film 102 as shown in FIG. 5.
Depositions 124, if accumulated in this manner, serve as masks to inhibit the progression of the plasma etching thereunder. Thus, when ARC film 118 in via hole 117 is removed after the completion of the simultaneous etching of ARC film 118 and upper interlayer film 102, a disadvantage of remaining depositions 124 around the opening of via hole 117 occurs as shown in FIG. 6.
Such depositions 124 remaining around the opening of via hole 117 prevent the formation of upper metal wiring 104 in a favorable shape, and result in defects such as breaks.
It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit in which no deposition remains around the opening of a via hole even when an upper interlayer film and an organic film are simultaneously plasma etched with a dual damascene method for forming a concave groove on the via hole.
In an aspect of the method of manufacturing a semiconductor integrated circuit of the present invention, when an upper interlayer film and the material of an organic film embedded in a via hole formed in the upper interlayer film are simultaneously plasma etched through an opening in a resist mask, the etching rate for the organic film material with an etching gas is higher than the etching rate for the upper interlayer film. Therefore, since the plasma etching does not proceed in a state in which the material of the organic film projects from the bottom of a concave groove formed in the upper interlayer film, and the production of depositions is prevented.
With aforementioned relationship of the etching rates, the plasma etching proceeds in a state in which the organic film material is dented from the bottom of the concave groove formed in the upper interlayer film. However, depositions tend to accumulate in terms of properties on the sides of the dent in the upper interlayer film.
In another aspect of the method of manufacturing a semiconductor integrated circuit of the present invention, the etching gas comprises a molecular structure which produces no deposition. Thus, depositions do not accumulate at portions such as a difference in height formed when the upper interlayer film and the organic film are simultaneously plasma etched with the dual damascene method.
In another aspect of the present invention, the etching gas may include the number of atoms of fluorine contained in the molecular structure three times or more than the number of atoms of carbon. In this case, since the number of the fluorine atoms contained in the molecular structure of the etching gas is relatively large, the etching rate for the organic film is higher than the etching rate for the upper interlayer film in terms of properties. Since the number of the carbon atoms contained in the molecular structure of the etching gas is relatively small, depositions are unlikely to be produced. Such an etching gas may comprise xe2x80x9cCF4xe2x80x9d or xe2x80x9cC2F6xe2x80x9d, for example.
In another aspect of the present invention, the pressure in an atmosphere may be xe2x80x9c100 [mTorr]xe2x80x9d or more, even xe2x80x9c300 to 400 [mTorr]xe2x80x9d. In this case, since the high pressure of the etching gas increases the probability of the collision of ions, moving ions in various directions are produced to cause isotropic plasma etching, thereby sequentially removing depositions which may slightly accumulate.
The above and other objects, features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.